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2.7 V to 16.5 V Hot Swap Controller with Power-Fail Comparator ADM1172
FEATURES
Controls supply rails from 2.7 V to 16.5 V Allows protected board removal and insertion to a live backplane External sense resistor provides adjustable analog current limit with circuit breaker Peak fault current limited with fast response Charge pumped gate drive for external N-FET switch Power-fail comparator Automatic retry or latch-off during current fault Undervoltage lockout 8-lead, TSOT package
GENERAL DESCRIPTION
The ADM1172 is a hot swap controller that safely enables a printed circuit board to be removed and inserted to a live backplane. This is achieved using an external N-channel power MOSFET with a current control loop that monitors the load current through a sense resistor. An internal charge pump is used to enhance the gate of the N-channel FET. When an overcurrent condition is detected, the gate voltage of the FET is reduced to limit the current flowing through the sense resistor. During an overcurrent condition, the TIMER pin capacitor determines the amount of time the FET remains at a current limiting mode of operation until it is shut down. The ON (ON-CLR) pin is the enable input for the device and can be used to monitor the input supply voltage. The ADM1172 operates with a supply voltage ranging from 2.7 V to 16.5 V. The ADM1172 also features a power-fail comparator. The voltage on the PFI pin is compared with an internal 0.6 V reference, and the output of this comparator is presented on the PFO pin. This device is available in two options: the ADM1172-1 with automatic retry for overcurrent fault and the ADM1172-2 with latch-off for an overcurrent fault. Toggling the ON (ON-CLR) pin resets a latched fault. The ADM1172 is packaged in an 8-lead TSOT.
APPLICATIONS
Hot swap board insertion: line cards, raid systems Industrial high-side switches/circuit breakers Electronic circuit breakers
FUNCTIONAL BLOCK DIAGRAM
VIN = 5V LONG RSENSE Q1 VOUT = 5V CLOAD VCC ON SENSE GATE PFI RON2 PFO TIMER CTIMER GND LONG GND GND RPR2
05126-001
SHORT
RON1
RPR1
ADM1172-1
Figure 1.
Rev. 0
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ADM1172 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Thermal Characteristics .............................................................. 4 ESD Caution.................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 12 Overview...................................................................................... 12 UVLO........................................................................................... 12 ON (ON-CLR) Pin..................................................................... 12 GATE ........................................................................................... 12 Current Limit Function............................................................. 12 Calculating the Current Limit .................................................. 12 Circuit Breaker Function........................................................... 12 Timer Function........................................................................... 13 Power-Up Timing Cycle ............................................................ 13 Circuit Breaker Timing Cycle................................................... 13 Automatic Retry or Latched Off............................................... 14 Power-Fail Comparator ............................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
7/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM1172 SPECIFICATIONS
VCC = 2.7 V to 16.5 V, TA = -40C to +85C, typical values at TA = 25C, unless otherwise noted. Table 1.
Parameter VCC PIN Operating Voltage Range Supply Current Undervoltage Lockout Undervoltage Lockout Hysteresis ON (ON-CLR) PIN Input Current Threshold Threshold Hysteresis SENSE PIN Hot Swap Operating Range Input Current Circuit Breaker Limit Voltage GATE PIN Drive Voltage Symbol VCC ICC VUVLO VUVLOHYS IINON VON VONHYST Min 2.7 2.4 0.65 2.525 40 0 1.3 50 Typ Max 16.5 0.8 2.65 Unit V mA V mV A V mV V A mV V V V V V A mA mA A A A A V V V mV A A V s s s Conditions
VCC rising
-1 1.22
+1 1.38
ON rising
IINSENSE VCB VGATE
2.7 5 44 4.6 6.0 8.75 7.5 5.56 -6.5
10 50 7.5 8 10 9 8 -12 4 25 -5 -60 2 100 1.3 0.2 0.6 10 0 -5
16.5 15 56 10 12 12 12 12 -14.5
VCB = (VCC - VSENSE) VGATE - VCC, VCC = 3.0 V VGATE - VCC, VCC = 3.3 V VGATE - VCC, VCC = 5 V VGATE - VCC, VCC = 12 V VGATE - VCC, VCC = 15 V VGATE = 0 V VGATE = 3 V, VCC = 5 V, ON (ON-CLR) = low VGATE = 3 V, VCC < UVLO Initial cycle, VTIMER = 1 V During current fault, VTIMER = 1 V After Cct breaker tip, VTIMER = 1 V Normal operation, VTIMER = 1 V TIMER rising TIMER falling
Pull-Up Current Pull-Down Current Pull-Down Current TIMER PIN Pull-Up Current Pull-Down Current Threshold High Threshold Low PFI PIN Threshold Rising Threshold Hysteresis Input Current PFO PIN Pull-Up Current Output Low Voltage tOFF Turn-Off Time (TIMER Rise to GATE Fall) Turn-Off Time (ON Fall to GATE Fall) Turn-Off Time (VCC Fall to IC Reset)
ITIMERUP ITIMERDN VTIMERH VTIMERL
-2 -25
-8.5 -100 3.5 1.38 0.25 0.62 +1
1.22 0.15 0.58 -1
0.4 2 40 40
ILOAD = 200 A VTIMER = 0 V to 2 V step, VCC = VON = 5 V VON = 5 V to 0 V step, VCC = 5 V VCC = 5 V to 2 V step, VON = 5 V
Rev. 0 | Page 3 of 16
ADM1172 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC Pin SENSE Pin VCC - SENSE TIMER Pin ON (ON-CLR) Pin PFI Pin PFO Pin GATE Pin Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec) Junction Temperature Rating -0.3 V to +20 V -0.3 V to +20 V 5 V -0.3 V to (VCC + 0.3 V) -0.3 V to +20 V -0.3 V to +20 V -0.3 V to +20 V -0.3 V to (VCC + 11 V) -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 8-Lead TSOT JA 152.9 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADM1172 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1172-1AUJ
TIMER 1 GND 2
8
ADM1172-2AUJ
VCC TIMER 1 GND 2
05126-006
8
VCC
ON 4
5
GATE
ON-CLR 4
5
GATE
Figure 2. Pin Configuration, 1AUJ Model
Figure 3. Pin Configuration, 2AUJ Model
Table 4. Pin Function Descriptions
Pin No. 1 Mnemonic TIMER Description Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing delay is 272.9 ms/F, and 21.7 ms/F for a circuit breaker delay. When the TIMER pin is pulled beyond the upper threshold, the GATE turns off. Chip Ground Pin. Power-Fail Comparator Output. Digital output from the power-fail comparator. Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV hysteresis and a glitch filter. The ADM1172 is reset when the ON (ON-CLR) pin is low. When the ON (ON-Error!) pin is high, the ADM1172 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model, the ADM1172-2. Gate Output Pin. An internal charge pump provides a 12 A pull-up current to drive the gate of an N-channel MOSFET. In an overcurrent condition, the ADM1172 controls the external FET to maintain a constant load current. Power-Fail Comparator Input. Comparator threshold = 0.6 V. Current Limit Sense Input Pin. The current limit is set via a sense resistor between the VCC and SENSE pins. In an overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the VCC pin and SENSE pin together. Positive Supply Input Pin. The ADM1172 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO) circuit with a glitch filter resets the ADM1172 when the supply voltage drops below the specified UVLO limit.
2 3 4
GND PFO ON (ON-CLR)
5
GATE
6 7
PFI SENSE
8
VCC
Rev. 0 | Page 5 of 16
05126-007
7 SENSE TOP VIEW PFO 3 (Not to Scale) 6 PFI
7 SENSE TOP VIEW PFO 3 (Not to Scale) 6 PFI
ADM1172 TYPICAL PERFORMANCE CHARACTERISTICS
0.50 0.45 0.40
SUPPLY CURRENT (mA) UVLO THRESHOLD (V)
2.65 2.63 2.61 2.59 2.57 2.55 2.53 2.51 2.49 2.47
05126-023
VCC = 5V VCC RISING
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
VCC FALLING
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 4. Supply Current vs. Supply Voltage (GATE Off)
0.8 0.7 20 0.6 0.5 0.4 0.3 0.2 5 0.1 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) 0 0 25
Figure 7. UVLO Threshold vs. Temperature
SUPPLY CURRENT (mA)
GATE VOLTAGE (V)
15
10
05126-024
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
Figure 5. Supply Current vs. Supply Voltage (GATE On)
1.0 0.9 0.8 20 VCC = 15V 0.6 0.5 0.4 VCC = 5V 0.3 0.2 0.1
05126-033
Figure 8. GATE Voltage vs. Supply Voltage
25 VCC = 15V
SUPPLY CURRENT (mA)
GATE VOLTAGE (V)
0.7
VCC = 12V
VCC = 12V 15 VCC = 5V 10 VCC = 3V 5
VCC = 3V
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. Supply Current vs. Temperature
Figure 9. GATE Voltage vs. Temperature
Rev. 0 | Page 6 of 16
05126-015
0 -50
0 -50
05126-013
05126-046
2.45 -50
ADM1172
10 9 0 -1 -2 -3 VCC = 5V
DELTA GATE VOLTAGE (V)
8 7 6 5 4 3 2 1
05126-014
ITIMERUP (A)
-4 -5 -6 -7 -8 -9
0
2
4
6
8
10
12
14
16
18
-25
0
25
50
75
100
125
150
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
Figure 10. Delta GATE Voltage vs. Supply Voltage
10 9 VCC = 12V VCC = 5V -20
Figure 13. ITIMERUP (In Initial Cycle) vs. Temperature
TA = 25C -30 -40
DELTA GATE VOLTAGE (V)
8 7 6 5 4 3 -80 2 1
05126-016
VCC = 15V
ITIMERUP (A)
-50 -60 -70
VCC = 3V
-90 -100 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 11. Delta GATE Voltage vs. Temperature
0 -1 -2 TA = 25C
Figure 14. ITIMERUP (During Cct Breaker Delay) vs. Supply Voltage
-20 VCC = 5V -30 -40
-3
ITIMERUP (A)
-4 -5 -6 -7
ITIMERUP (A)
-50 -60 -70 -80
-8 -9
05126-035
-90 -100 -50
0
2
4
6
8
10
12
14
16
18
-25
0
25
50
75
100
125
150
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
Figure 12. ITIMERUP (In Initial Cycle) vs. Supply Voltage
Figure 15. ITIMERUP (During Cct Breaker Delay) vs. Temperature
Rev. 0 | Page 7 of 16
05126-039
-10
05126-036
0 -50
05126-038
0
-10 -50
ADM1172
3.0 2.8 2.6 2.4 TA = 25C 1.36 1.38 VCC = 5V
TIMER HIGH THRESHOLD (V)
05126-034
1.34 1.32 1.30 1.28 1.26 1.24 1.22 -50
ITIMERDN (A)
2.2 2.0 1.8 1.6 1.4 1.2 1.0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 16. ITIMERDN (In Cool-Off Cycle) vs. Supply Voltage
3.0 2.8 2.6 2.4 VCC = 5V 0.23 0.24
Figure 19. TIMER High Threshold vs. Temperature
TA = 25C
TIMER LOW THRESHOLD (V)
0.22 0.21 0.20 0.19 0.18 0.17 0.16 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
ITIMERDN (A)
2.2 2.0 1.8 1.6 1.4 1.2
05126-037
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 17. ITIMERDN (In Cool-Off Cycle) vs. Temperature
1.38 TA = 25C 1.36 0.23 0.24
Figure 20. TIMER Low Threshold vs. Supply Voltage
VCC = 5V
TIMER HIGH THRESHOLD (V)
1.34 1.32 1.30 1.28 1.26 1.24 1.22 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
TIMER LOW THRESHOLD (V)
0.22 0.21 0.20 0.19 0.18 0.17 0.16 -50
05126-042
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 18. TIMER High Threshold vs. Supply Voltage
Figure 21. TIMER Low Threshold vs. Temperature
Rev. 0 | Page 8 of 16
05126-045
05126-043
1.0 -50
05126-044
ADM1172
1.45 TA = 25C 1.40 70 HIGH THRESHOLD 60 80
ON (ON-CLR) PIN THRESHOLD (V)
1.35 1.30
tOFF(ONLOW) (s)
VCC = 15V 50 40 VCC = 5V 30 VCC = 3V 20 10 0 -50 VCC = 12V
LOW THRESHOLD 1.25 1.20 1.15 1.10 1.05 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
05126-040
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 22. ON (ON-CLR) Pin Threshold vs. Supply Voltage
1.45 VCC = 5V 1.40 50 49 48 1.35 1.30 1.25 1.20 1.15 42 1.10 1.05 -50 41
05126-041
Figure 25. tOFF(ONLOW) vs. Temperature
ON (ON-CLR) PIN THRESHOLD (V)
HIGH THRESHOLD 47
LOW THRESHOLD
VCB (mV)
46 45 44 43
-25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
18
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
Figure 23. ON (ON-CLR) Pin Threshold vs. Temperature
80 TA = 25C 70 60 35 50 45 40
Figure 26. Cct Breaker Voltage vs. Supply Voltage
tOFF(ONLOW) (s)
50 40 30 20
VCB (mV)
30 25 20 15 10
10 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
5
05126-047
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 24. tOFF(ONLOW) vs. Supply Voltage
Figure 27. Cct Breaker Voltage vs. Temperature
Rev. 0 | Page 9 of 16
05126-021
0 -50
05126-049
40
05126-048
ADM1172
12 0.620 0.615 10 0.610
GATE CURRENT (mA)
8
PFI THRESHOLD (V)
0.605 HIGH THRESHOLD 0.600 0.595 LOW THRESHOLD 0.590
6
4
2
0.585 0.580 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V)
05126-008
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
Figure 28. GATE Current (Down) vs. Supply Voltage
-8 0.610
Figure 31. PFI Threshold vs. Supply Voltage
-9
0.605 HIGH THRESHOLD
GATE CURRENT (A)
PFI THRESHOLD (V)
-10
0.600
-11
0.595 LOW THRESHOLD 0.590
-12
-13
0.585
05126-009
0
2
4
6
8
10
12
14
16
18
0
50 TEMPERATURE (C)
100
150
SUPPLY VOLTAGE (V)
Figure 29. GATE Current (Up) vs. Supply Voltage
Figure 32. PFI Threshold vs. Temperature
-11.0 -11.2
-3.0 -3.5
PFO PULL-UP CURRENT (A)
-11.4
-4.0 VCC = 5V -4.5 VCC = 3V -5.0 -5.5 -6.0 -6.5 VCC = 15V -7.0 VCC = 12V -7.5
GATE CURRENT (A)
-11.6 -11.8 -12.0 VCC = 5V -12.2 VCC = 12V -12.4 -12.6 -12.8
05126-017
VCC = 3V
VCC = 15V
-25
0
25
50
75
100
125
150
0
50 TEMPERATURE (C)
100
150
TEMPERATURE (C)
Figure 30. GATE Current (up) vs. Temperature
Figure 33. PFO Pull-Up Current vs. Temperature
Rev. 0 | Page 10 of 16
05126-027
-13.0 -50
-8.0 -50
05126-026
-14
0.580 -50
05126-025
0
ADM1172
0.25
0.14 0.12
VCC = 3V VCC = 12V
0.20
0.10
PFO VOL (V)
PFO VOL (V)
0.15 VCC = 15V 0.10
0.08 0.06 0.04
VCC = 3V VCC = 15V
VCC = 5V 0.05
VCC = 12V 0.02
I = 300A
05126-028
VCC = 5V
I = 100A
150
0
50 TEMPERATURE (C)
100
0
50 TEMPERATURE (C)
100
150
Figure 34. PFO Output Low Voltage vs. Temperature, I = 300 A
0.50 0.45
Figure 36. PFO Output Low Voltage vs. Temperature, I = 100 A
700 600 VCC = 3V
0.40 0.35 0.30 0.25 0.20 0.15 0.10
VCC = 3V
500
VCC = 12V
PFO VOL (mV)
PFO VOL (V)
400
VCC = 12V
VCC = 5V
VCC = 15V VCC = 5V
300
VCC = 15V
200 100
0.05 I = 500A
05126-029
0
50 TEMPERATURE (C)
100
150
0.1
0.3
0.5 ILOAD (mA)
0.7
0.9
1.1
Figure 35. PFO Output Low Voltage vs. Temperature, I = 500 A
Figure 37. PFO Output Low Voltage vs. Load Current
Rev. 0 | Page 11 of 16
05126-031
0 -50
0 -0.1
05126-030
0 -50
0 -50
ADM1172 THEORY OF OPERATION
Many systems require the insertion or removal of circuit boards to live backplanes. During this event, the supply bypass and holdup capacitors can require substantial transient currents from the backplane power supply as they charge. These currents can cause permanent damage to connector pins or undesirable glitches and resets to the system. The ADM1172 is intended to control the powering of a system (on and off) in a controlled manner, allowing the board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM1172 can reside either on the backplane or on the removable board. delay time at card insertion. If using a short pin system to enable the device, a pull-down resistor should be used to hold the device prior to insertion.
GATE
Gate drive for the external N-channel MOSFET is achieved using an internal charge pump. The gate driver consists of a 12 A pull-up from the internal charge pump. There are various pull-down devices on this pin. At a hotswap condition the board is hot inserted to the supply bus. During this event, it is possible for the external FET GATE capacitance to be charged up by the sudden presence of the supply voltage. This can cause uncontrolled inrush currents. An internal strong pull-down circuit holds GATE low while in UVLO. This reduces current surges at insertion. After the initial timing cycle, the GATE is then pulled high. During an overcurrent condition, the ADM1172 servos the GATE pin in an attempt to maintain a constant current to the load until the circuit breaker timeout completes. In the event of a timeout, the GATE pin abruptly shuts down using the 4 mA pull-down device. Care must be taken not to load the GATE pin resistively because this reduces the gate drive capability.
OVERVIEW
The ADM1172 operates over a supply range of 2.7 V to 16.5 V. As the supply voltage is coming up, an undervoltage lockout circuit checks if sufficient supply voltage is present for proper operation. During this period, the FET is held off by the GATE pin being held to GND. When the supply voltage reaches a level above UVLO and the ON (ON-CLR) pin is high, an initial timing cycle ensures that the board is fully inserted in the backplane before turning on the FET. The TIMER pin capacitor sets the periods for all of the TIMER pin functions. After the initial timing cycle, the ADM1172 monitors the inrush current through an external sense resistor. Overcurrent conditions are actively limited to 50 mV/RSENSE for the circuit breaker timer limit. The ADM1172-1 automatically retries after a current limit fault and the ADM1172-2 latches off. The retry duty cycle on the ADM1172-1 timer function is limited to 3.8% for FET cooling.
CURRENT LIMIT FUNCTION
The ADM1172 features a fast response current control loop that actively limits the current by reducing the gate voltage of the external FET. This current is measured by monitoring the voltage drop across an external sense resistor. The ADM1172 tries to regulate the gate of the FET to achieve a 50 mV voltage drop across the sense resistor.
UVLO
If the VCC supply is too low for normal operation, an undervoltage lockout circuit holds the ADM1172 in reset. The GATE pin is held to GND during this period. When the supply reaches this UVLO voltage, the ADM1172 starts when the ON (ON-CLR) pin condition is satisfied.
CALCULATING THE CURRENT LIMIT
The sense resistor connected between VCC and the SENSE pin is used to determine the nominal fault current limit. This is given by the following equation: ILIMITNOM = VCBNOM/RSENSENOM The minimum load current is given by Equation 2 ILIMITMIN = VCBMIN/RSENSEMAX The maximum load current is given by Equation 3. ILIMITMAX = VCBMAX/RSENSEMIN (1) (2) (3)
ON (ON-CLR) PIN
The ON (ON-CLR) pin is the enable pin. It is connected to a comparator that has a low-to-high threshold of 1.3 V with 80 mV hysteresis and a glitch filter. The ADM1172 is reset when the ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is high, the ADM1172 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model, the ADM1172-2. A low input on the ON (ON-CLR) pin turns off the external FET by pulling the GATE pin to ground and resets the timer. An external resistor divider at the ON (ON-CLR) pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit. There is a glitch filter delay of approximately 3 s on rising allowing the addition of an RC filter at the ON (ON-CLR) pin to increase the
For proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. The sense resistor power rating must exceed (VCBMAX)2/RSENSEMIN
CIRCUIT BREAKER FUNCTION
When the supply experiences a sudden current surge, such as a low impedance fault on load, the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected, potentially causing system malfunctions. The ADM1172 limits the current drawn by the fault by reducing the
Rev. 0 | Page 12 of 16
ADM1172
gate voltage of the external FET. This minimizes the bus supply voltage drop caused by the fault and protects neighboring cards. As the voltage across the sense resistor approaches the current limit, a timer activates. This timer resets again if the sense voltage returns below this level. If the sense voltage is any voltage below 44 mV, the timer is guaranteed to be off. Should the current continue to increase, the ADM1172 tries to regulate the gate of the FET to achieve a limit of 50 mV across the sense resistor. However, if the device is unable to regulate the fault current and the sense voltage further increases, a larger pulldown, in the order of milliamperes, is enabled to compensate for fast current surges. If the sense voltage is any voltage greater than 56 mV, this pull-down is guaranteed to be on. When the timer expires, the GATE pin shuts down. When the initial cycle ends, a start-up cycle activates and the GATE pin is pulled high; the TIMER pin continues to pull down.
VIN 1 VON 2 VTIMER 3 4
VGATE
VOUT
TIMER FUNCTION
The TIMER pin is responsible for several key functions on the ADM1172. A capacitor controls the initial power on reset time and the amount of time an overcurrent condition lasts before the FET shuts down. On the ADM1172-1, the timer pin also controls the time between auto retry pulses. There are pull-up and pull-down currents internally available to control the timer functions. The voltage on the TIMER pin is compared with two threshold voltages: COMP1 (0.2 V) and COMP2 (1.3 V). The four timing currents are listed in Table 5. Table 5.
Timing Current Pull-up Pull-up Pull-down Pull-down Level (A) 5 60 2 100
VTIMER 100A VGATE RESET MODE INITIAL CYCLE START-UP CYCLE NORMAL CYCLE
05126-002
Figure 38. Power-Up Timing
VIN
VON
60A 5A 2A
VOUT
POWER-UP TIMING CYCLE
The ADM1172 is in reset when the ON (ON-CLR) pin is held low. The GATE pin is pulled low and the TIMER pin is pulled low with a 100 A pull-down. At Time Point 2 in Figure 38, the ON (ON-CLR) pin is pulled high. For the device to startup correctly, the supply voltage must be above UVLO, the ON (ON-CLR) pin must be above 1.3 V, and the TIMER pin voltage must be less than 0.2 V. The initial timing cycle begins when these three conditions are met, and the TIMER pin is pulled high with 5 A. At Time Point 3, the TIMER reaches the COMP2 threshold. This is the end of the first section of the initial cycle. The 100 A current source then pulls down the TIMER pin until it reaches 0.2 V at Time Point 4. The initial cycle delay (Time Point 2 to Time Point 4) relates to CTIMER by equation tINITIAL = 1.3 x CTIMER/5 A (4)
IRSENSE
RESET MODE
INITIAL START-UP CYCLE CYCLE
NORMAL CYCLE
Figure 39. Power-Up into Capacitor
CIRCUIT BREAKER TIMING CYCLE
When the voltage across the sense resistor exceeds the circuit breaker trip voltage, the 60 A timer pull-up current is activated. If the sense voltage falls below this level before the TIMER pin reaches 1.3 V, the 60 A pull-up is disabled and the 2 A pulldown is enabled. This is likely to happen if the overcurrent fault is only transient, such as an inrush current. This is shown in Figure 39. However, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 A pull-up remains active. This allows the TIMER pin to reach the high trip point of 1.3 V and initiate the GATE shutdown. On the ADM1172-2, the TIMER pin continues pulling up but switches to the 5 A pull-up when it reaches the 1.3 V
Rev. 0 | Page 13 of 16
05126-003
ADM1172
threshold. The device can be reset by toggling the ON-CLR pin or by manually pulling the TIMER pin low. On the ADM1172-1, the TIMER pin activates the 2 A pull-down once the 1.3 V threshold is reached, and continues to pull down until it reaches the 0.2 V threshold. At this point, the 100 A pull-down is activated and the GATE pin is enabled. The device keeps retrying in the manner as shown in Figure 40. The duty cycle of this automatic retry cycle is set to the ratio of 2 A/60 A, which approximates 3.8% on. The value of the timer capacitor determines the on time of this cycle. This time is calculated as follows: tON = 1.3 x CTIMER/60 A tOFF = 1.1 x CTIMER/2 A
IRSENSE VGSFET SHORTCIRCUIT EVENT COMP2 COMP1
05126-005
The ADM1172-2 model has a latch off system whereby when a current fault is detected, the GATE is switched off after a time determined by the timer capacitor (see Figure 41 for details). Toggling the ON-CLR pin, or pulling the TIMER pin to GND for a brief period, resets this condition.
IRSENSE
5A
VTIMER 60A
VOUT
2A
VTIMER 60A 100A VGSFET SHORTCIRCUIT EVENT COMP2 FAULT CYCLE COMP1 FAULT CYCLE
Figure 41. ADM1172-2 Latch Off After Overcurrent Fault
POWER-FAIL COMPARATOR
The ADM1172 has an integrated comparator that can be used as a power-fail/OV/UV detector. The comparator has a 0.6 V reference, and it is designed to be active high when the voltage on the PFI pin drops to below this threshold. The only action that results from the PFI pin tripping the comparator is the change of state on the PFO pin. The PFI pin can be used to monitor the supply on either side of the FET, for an OV or UV condition set by a resistor divider network. The PFO can then be sent to a control system and used as a power-good/power-fail signal. The PFO output has a 5 A internal pull-up. A 10 k resistor is recommended on the PFO pin to ensure that it is either pulled up or down during power-up. The pin is in high impedance while VCC < UVLO and can result in invalid powerfail signals.
VOUT
Figure 40. ADM1172-1 Automatic Retry During Overcurrent Fault
AUTOMATIC RETRY OR LATCHED OFF
The ADM1172 is available in two models. The ADM1172-1 has an automatic retry system whereby when a current fault is detected, the FET is shut down after a time determined by the timer capacitor, and it is switched on again in a controlled continuous cycle to determine if the fault remains (see Figure 40 for details). The period of this cycle is determined by the timer capacitor at a duty cycle of 3.8% on and 96.2% off.
05126-004
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ADM1172 OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 INDICATOR 0.65 BSC *0.90 0.87 0.84 1.95 BSC
*1.00 MAX 0.38 0.22
0.20 0.08 8 4 0
0.10 MAX
SEATING PLANE
0.60 0.45 0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 42. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM1172-1AUJZ-RL7 1 ADM1172-2AUJZ-RL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 8-Lead TSOT 8-Lead TSOT
Package Option UJ-8 UJ-8
Branding M1M M1N
Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADM1172 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05126-0-7/06(0)
Rev. 0 | Page 16 of 16

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